STM32 Timer Calculator: PSC and ARR for Any Frequency
Find the prescaler (PSC) and auto-reload (ARR) values that make an STM32 timer run at the frequency or period you need. You get two answers: the pair with the most PWM resolution and the round-number pair most engineers write by hand, each with the real frequency, the error in ppm, the tick period and the compare value (CCR) for your duty cycle. Every input lives in the URL, so a copied link reproduces the calculation.
The smallest prescaler that keeps ARR in range, so the period has as many counts as this clock allows.
- Real frequency
- 1 kHz
- period 1 ms
- Error
- exact
- whole-number division
- Tick period
- 27.78 ns
- counter clock 36 MHz
- PWM resolution
- 15.1 bits
- 36000 counts, 0.0028% duty steps
A prescaler that makes one count exactly 1 µs, the way it is usually set by hand.
- Real frequency
- 1 kHz
- period 1 ms
- Error
- exact
- whole-number division
- Tick period
- 1 µs
- counter clock 1 MHz
- PWM resolution
- 10.0 bits
- 1000 counts, 0.1% duty steps
Both settings give the same update rate. PSC = 71 makes one count 1 µs, so ARR and the compare values read as time. PSC = 1 keeps 36000 counts per period, which only matters if the timer also does PWM or input capture.
The link reproduces these exact inputs - paste it in a design review or a pull request.
Bring the part number, the clock tree and what the signal has to do. We will look at the timer plan with you (PWM, input capture, motor control or low-power wake-ups) before it is buried in the firmware. If you need the whole thing built, see firmware development services.
PSC for a round tick at common timer clocks
The prescaler value that turns each timer clock into a 1 µs, 100 µs or 1 ms count. Where the clock is not a whole number of megahertz the nearest value is shown with the tick it really gives. Above 65.536 MHz a 1 ms tick needs a prescaler past 65535 and cannot be set. The last column is the longest period a 16-bit timer reaches, with PSC and ARR both at 65535.
| Timer clock | PSC for 1 µs | PSC for 100 µs | PSC for 1 ms | Longest 16-bit period | Where you meet it |
|---|---|---|---|---|---|
| 2.097152 MHz | 1 (953.7 ns) | 209 (100.1 µs) | 2096 (999.9 µs) | 2048 s | MSI default on L0 and L1 |
| 8 MHz | 7 | 799 | 7999 | 536.9 s | HSI on F0, F1 and F3 |
| 16 MHz | 15 | 1599 | 15999 | 268.4 s | HSI on F4, F7, G0 and G4 |
| 48 MHz | 47 | 4799 | 47999 | 89.48 s | F0 at full speed |
| 72 MHz | 71 | 7199 | over 65535 | 59.65 s | F103 and F303 at full speed |
| 84 MHz | 83 | 8399 | over 65535 | 51.13 s | F401 at full speed, APB1 timers on a 168 MHz F407 |
| 100 MHz | 99 | 9999 | over 65535 | 42.95 s | F411 at full speed |
| 170 MHz | 169 | 16999 | over 65535 | 25.26 s | G4 at full speed |
| 216 MHz | 215 | 21599 | over 65535 | 19.88 s | F7 APB2 timers at full speed |
The equation
A timer counts ticks of its own clock. The prescaler divides the timer clock by PSC + 1 to make the tick, and the counter then runs from 0 up to ARR, which is ARR + 1 ticks, before it rolls over with an update event. So f_update = f_tim / ((PSC + 1) × (ARR + 1)). Both registers hold one less than the number they divide by, and forgetting that is the classic mistake: at 72 MHz, writing 72 and 1000 instead of 71 and 999 gives 985.316 Hz, about 1.5% slow and close enough to pass a quick look on a scope. Any pair whose product is f_tim / f_target gives the same frequency, so there are usually many right answers, and the calculator shows the two worth having. PSC is 16 bits on every general-purpose and advanced timer. ARR is 16 bits on most timers and 32 bits on a few, TIM2 and TIM5 on many families. ARR = 0 stops the counter, so the fastest a timer runs is half its clock.
The same arithmetic applies to any microcontroller timer with a prescaler and a period register, whatever the vendor calls them. STM32 is a trademark of STMicroelectronics; this tool is independent and is not affiliated with or endorsed by them.
The timer clock is not always the bus clock
The number to enter is the clock the timer counts, not the APB bus clock next to it in the clock tree. On most STM32 families, when the APB prescaler is anything other than 1, the timers on that bus run at twice the bus clock. The classic case is an F103 at 72 MHz: APB1 is limited to 36 MHz, but TIM2 to TIM4 count at 72 MHz. Work the numbers from 36 MHz and you get PSC = 35 and ARR = 999, and a timer that runs at 2 kHz instead of 1 kHz. Some families add a TIMPRE bit that changes the multiplier again, so read the timer clock from the clock tree in the reference manual or the clock view in STM32CubeMX instead of assuming it.
Resolution or round numbers
The smallest prescaler leaves the most counts in a period, and counts are PWM resolution: the duty cycle can only move one count at a time. In PWM mode 1 on an up-counting timer the output is active while CNT is below CCR, so CCR = 0 is 0% and 100% needs CCR = ARR + 1, one more than the period register. At 20 kHz from an 84 MHz clock, PSC = 0 gives 4200 counts, 12.0 bits. Prescale the same timer to a tidy 1 µs tick and ARR drops to 49: 50 counts, 5.6 bits, 2% per step. For an interrupt tick none of that matters, and the round setting is easier to read in code because ARR and the compare registers are then in microseconds. For PWM, for input capture and for anything that measures time, take the small prescaler. Centre-aligned mode counts up and back down, so the same PWM frequency needs half the ARR and gives one bit less. Motor drives accept that because the pulses are symmetric and the phase current can be sampled at the centre, away from the switching edges.
When the frequency cannot be exact
A timer divides its clock by a whole number, so only frequencies of the form f_tim / N exist. If f_tim / f_target is not whole, something has to round. Without a prescaler the worst case is half a count of ARR: 44.1 kHz from 72 MHz wants a division of 1632.65, gets 1633, and lands at 44.0906 kHz, 212 ppm low. Once the target is slow enough to need a prescaler, a 16-bit ARR sits above half scale and rounding it costs under 16 ppm, comparable to a crystal's own tolerance: 440 Hz from 72 MHz comes out at 440.004 Hz, 8.33 ppm high. The calculator looks for an exact pair first, starting at the smallest prescaler and trying up to eight times that, so an exact frequency never costs more than three bits of resolution. Only then does it round, and it states the error in ppm either way.
One practical note for changing these values on the fly: the prescaler register is buffered, so a new PSC takes effect at the next update event, and ARR is buffered only when the ARPE bit is set.
Frequently asked questions
How do I calculate PSC and ARR for an STM32 timer?
Divide the timer clock by the frequency you want. That is the total division, and (PSC + 1) × (ARR + 1) must equal it. For 1 kHz from a 72 MHz timer clock the total is 72000. Pick a prescaler that leaves ARR inside its 16-bit range, then ARR = total / (PSC + 1) - 1. PSC = 71 makes a 1 µs tick and ARR = 999; PSC = 1 and ARR = 35999 give the same 1 kHz with 36 times the resolution. Both registers hold one less than the number they divide by, and the clock to use is the timer clock, which is twice the APB clock whenever the APB prescaler is not 1.
What prescaler and ARR give 1 kHz at 72 MHz?
PSC = 71 and ARR = 999 is the setting most people write by hand: the prescaler divides 72 MHz down to a 1 MHz counter clock, one count per microsecond, and 1000 counts make 1 ms. It is exact. If the same timer also drives PWM, PSC = 1 and ARR = 35999 is the better pair: still exactly 1 kHz, but 36000 counts per period (15.1 bits) instead of 1000 (10.0 bits). On a 32-bit timer, PSC = 0 and ARR = 71999 works too.
How do I set up 50 Hz servo PWM on STM32?
At a 72 MHz timer clock, PSC = 71 and ARR = 19999 give a 1 µs tick and a 20 ms period, exactly 50 Hz. The compare value is then the pulse width in microseconds: CCR = 1000 for 1 ms, 1500 for centre, 2000 for 2 ms. A servo only uses 5 to 10% of the period, so that is 1000 steps of travel. For finer steps use PSC = 23 and ARR = 59999: the tick becomes 333.3 ns and the same 1 to 2 ms range runs from CCR 3000 to 6000, which is 3000 steps. Use PWM mode 1, so the output is high while the counter is below CCR.
What PWM resolution do I get at 20 kHz?
With no prescaler, the timer clock divided by the PWM frequency. At 20 kHz that is 800 counts (9.6 bits) from 16 MHz, 3600 counts (11.8 bits) from 72 MHz, 4200 counts (12.0 bits) from 84 MHz and 8500 counts (13.1 bits) from 170 MHz. At 84 MHz one count is a duty step of 0.024%. Centre-aligned mode halves it: ARR = 2100 at 84 MHz, 11.0 bits. A prescaler throws resolution away: a 1 µs tick at 84 MHz leaves ARR = 49, only 50 counts and 2% steps.
Why is my STM32 timer running at twice the expected frequency?
Almost always because the calculation used the APB bus clock instead of the timer clock. When the APB prescaler is not 1, most STM32 families clock the timers on that bus at twice the bus frequency. An F103 at 72 MHz has a 36 MHz APB1, but TIM2 to TIM4 count at 72 MHz: PSC = 35 and ARR = 999, worked out from 36 MHz, give 2 kHz instead of 1 kHz. PSC = 71 is the fix. The other cause is centre-aligned mode, where update events fire at both ends of the count, so an update interrupt runs at twice the PWM frequency.
If the firmware is the product
Two timer registers are a five-minute decision. A motor drive, a capture chain that has to hold its timing over temperature, or a battery product where the timers decide the sleep current is not, and that is our day job: firmware development explains how we work. Still choosing the part? The MCU selector narrows it down. The RC filter calculator sizes the filter that turns a PWM output into a DC level, and the crystal load capacitor calculator covers the clock every number on this page depends on. If a number here decides something real, a free 30-minute technical call is the fastest way to check it against someone who has shipped the firmware.