RC Filter Calculator: Cutoff Frequency and Time Constant
Find the cutoff frequency and time constant of an RC low-pass or high-pass filter, or the standard resistor or capacitor value for a target cutoff. It also shows what the textbook formula leaves out: the gain and phase at any frequency, the settling time for an N-bit ADC, the attenuation at Nyquist, the corner over component tolerance, and what the source and the load do to it. Every input lives in the URL, so a copied link reproduces the calculation.
- Time constant τ
- 150 µs
- R × C
- Rise time, 10 to 90%
- 329.6 µs
- 2.197 τ, or 0.35 / fc
- Gain at 5 kHz
- -13.66 dB
- 0.208 of the input, phase -78.0°
- Settles to 1/2 LSB at 12 bits
- 1.352 ms
- 9.01 τ after a step
- Settles to 1% / 0.1%
- 690.8 µs / 1.036 ms
- 4.6 τ and 6.9 τ
- Cutoff over tolerance
- 1.001 kHz to 1.128 kHz
- ±1% R and ±5% C
- Attenuation at Nyquist
- 13.7 dB
- at 5 kHz, half the sample rate
- PWM ripple at 5 kHz
- 32.2%
- peak to peak, of the amplitude of a 50% duty square wave
At the 5 kHz Nyquist frequency (half of 10 kHz) this filter attenuates only 13.7 dB, so noise above Nyquist folds back into the samples almost untouched. One pole needs its corner at or below 502.5 Hz for 20 dB there. Lower the corner, sample faster and average, or add a second pole.
The link reproduces these exact inputs - paste it in a design review or a pull request.
Bring the signal, the sample rate and the accuracy you need. We will look at the front end with you (one pole or two, passive or active, how much to leave to firmware) before the board goes to fab. If you need the whole board done, see PCB design and layout services.
Time constants and how far a step has settled
The share of a step an RC circuit has covered after a number of time constants, 1 - e^(-t / τ), and how long that is for the filter above. A high-pass output has decayed by the same share.
| Time after the step | Settled | With your τ |
|---|---|---|
| 1 τ | 63.2% | 150 µs |
| 2 τ | 86.5% | 300 µs |
| 3 τ | 95.0% | 450 µs |
| 4.6 τ | 99.0% | 690.8 µs |
| 6.9 τ | 99.9% | 1.036 ms |
| 9.01 τ | within 1/2 LSB at 12 bits | 1.352 ms |
The equation
A resistor and a capacitor make a first-order filter with one corner frequency, fc = 1 / (2 × π × R × C), and one time constant, τ = R × C. Take the output across the capacitor and it is a low-pass, with |H| = 1 / √(1 + (f / fc)²) and a phase of -atan(f / fc). Take it across the resistor and it is a high-pass, with |H| = (f / fc) / √(1 + (f / fc)²) and a phase of 90° - atan(f / fc). Either way the output is 0.707 of the input (-3.01 dB) at the corner, and the slope beyond it is 20 dB per decade. In the time domain a step covers 63.2% of the distance in one time constant, and the 10% to 90% rise time is 2.197 × τ, which is the familiar 0.35 / fc. Give a target corner instead and the calculator picks the nearest standard resistor or capacitor value and reports the corner that value really gives.
One pole is a gentle filter
Twenty decibels per decade means a signal ten times above the corner still gets through at a tenth of its amplitude. That is plenty to take the edge off switching noise and far too little to be an anti-aliasing filter on its own: the default example on this page, 1.061 kHz in front of a converter sampling at 10 kHz, manages 13.7 dB at Nyquist. Getting 20 dB at Nyquist from a single pole takes a corner 9.95 times below it, and 40 dB takes a hundred times. The practical answers are to sample much faster than the signal needs and average in firmware, so the RC only has to deal with frequencies far above its corner, or to add a second pole. Enter your sample rate and the calculator states the attenuation at Nyquist rather than leaving you to assume it.
Settling time is the price of a low corner
Every decibel of filtering is paid for in response time. A step settles within 1% in 4.6 τ and within 0.1% in 6.9 τ, and a converter cares about its own resolution: half an LSB at N bits takes τ × ln(2^(N+1)), which is 9.01 τ at 12 bits and 11.78 τ at 16. If a multiplexer switches channels in front of the filter, or the signal steps, that is how long to wait before a reading can be trusted. The same trade governs PWM filtered into a DC level: the ripple falls in proportion to τ and the response slows in proportion to it, so the cheap win is always a higher PWM frequency. A debounce or a reset delay is a threshold crossing instead: the output reaches 70% of the step after 1.2 τ, which is 1.204 ms for 10 kΩ and 100 nF. Feed a slow edge like that into a Schmitt-trigger input, not a plain logic input.
The source and the load are part of the filter
The textbook formula assumes the filter is driven from zero ohms and looks into an open circuit. In a low-pass, source resistance adds to R, and a load across the capacitor does two things: it forms a divider that lowers the DC level, and it lowers the resistance the capacitor sees, which raises the corner. 10 kΩ and 100 nF into a 100 kΩ load give a DC gain of 0.909, 9.1% low, and a corner of 175.1 Hz instead of 159.2 Hz. For a 1% error the load has to be a hundred times R: into 1 MΩ the same filter is 0.99% low. Part tolerance is the other reality check. Capacitors are loose parts: a 1% resistor and a 10% capacitor put that 159.2 Hz corner anywhere from 143.3 to 178.6 Hz, and an X7R or X5R ceramic also loses capacitance under DC bias and over temperature, which moves the corner up. Use C0G/NP0 or film where the corner matters. In front of a SAR converter the capacitor has a second job as the charge reservoir for the sampling capacitor: by charge sharing alone, in the worst case of a sampling capacitor that starts a full scale away, the kick stays under one LSB when the external capacitor is 2^N times larger, which is 20.48 nF for 12 bits and 5 pF.
Frequently asked questions
How do I calculate the cutoff frequency of an RC filter?
Use fc = 1 / (2 × π × R × C), with R in ohms and C in farads. A 10 kΩ resistor and a 15 nF capacitor give 1 / (2 × π × 10,000 × 0.000000015) = 1.061 kHz. At that frequency the output is 0.707 of the input, which is -3.01 dB, and a low-pass output lags the input by 45°. The formula is the same for a low-pass (resistor in series, capacitor to ground) and a high-pass (capacitor in series, resistor to ground). Above the corner a low-pass falls 20 dB per decade: this one is at -20.04 dB at 10.61 kHz and -40 dB at 106.1 kHz.
What is the cutoff frequency of 10k and 100nF?
159.2 Hz, from 1 / (2 × π × 10 kΩ × 100 nF). The time constant is 10 kΩ × 100 nF = 1 ms, so a step takes 2.197 ms to rise from 10% to 90% and 4.605 ms to settle within 1%. A 1 kHz signal comes out at -16.07 dB, about 0.157 of its input amplitude. With a 1% resistor and a 10% capacitor the corner can land anywhere from 143.3 Hz to 178.6 Hz, which is why the capacitor's tolerance matters far more than the resistor's.
What RC filter do I need in front of an ADC?
Choose the corner between three limits. It has to sit above the fastest signal you want to measure, because a single pole already costs 3 dB at the corner. It has to sit well below half the sample rate, and one pole falls only 20 dB per decade: 10 kΩ and 15 nF (1.061 kHz) in front of a converter sampling at 10 kHz attenuate just 13.7 dB at the 5 kHz Nyquist frequency, and 20 dB there needs a corner at or below 502.5 Hz, or a faster sample rate. And the filter has to settle before you sample after a step or a multiplexer switch: settling within half an LSB at 12 bits takes 9.01 time constants, 1.352 ms for these parts.
How do I turn PWM into a DC voltage with an RC filter?
Use a low-pass with its corner far below the PWM frequency; the output then sits at the duty cycle times the PWM amplitude. For a first-order filter with the PWM frequency well above the corner, the peak-to-peak ripple at 50% duty, the worst case, is approximately Vpp / (4 × f_pwm × τ). With 1 kHz PWM, 10 kΩ and 1 µF give a 15.92 Hz corner and τ = 10 ms, so the ripple is about 2.5% of the PWM amplitude, 82.5 mV on 3.3 V logic, and the output needs 46.05 ms to settle within 1% after a duty change. Less ripple means a slower output, so raise the PWM frequency first, then add a second RC stage, and buffer the output if the load is not far higher than R.
What is the time constant of an RC circuit?
The time constant τ is R × C, in seconds when R is in ohms and C in farads: 10 kΩ × 100 nF = 1 ms. After one time constant a step has covered 63.2% of the way to its final value and after three 95.0%; it takes 4.6 τ to reach 99% and 6.9 τ to reach 99.9%. The time constant and the cutoff frequency carry the same information: fc = 1 / (2 × π × τ), so 1 ms corresponds to 159.2 Hz, and the 10% to 90% rise time is 2.197 × τ, or 0.35 / fc.
If the board is the product
An RC on one pin is a five-minute decision. A signal chain that has to hold its accuracy over temperature, layout and production spread is not, and that is our day job: PCB design and layout covers the hardware, and firmware development covers the sampling and filtering code on the other side of the pin. For the decisions next to this one, the voltage divider calculator sets the level in front of the filter, the STM32 timer calculator sets the PWM frequency, and the I2C pull-up calculator applies the same RC rise-time arithmetic to a bus. If a number here decides something real, a free 30-minute technical call is the fastest way to check it against someone who has shipped the board.