Crystal Load Capacitor Calculator with Gain Margin
Find C1 and C2 for a crystal from its load capacitance and your board's stray capacitance, rounded to a standard C0G value you can buy. It also shows the load that value really presents, the frequency error that follows in ppm, and whether the MCU's oscillator has the gain margin to start the crystal, the check ST's AN2867 asks for. Every input lives in the URL, so a copied link reproduces the calculation.
- Load the crystal sees
- 18 pF
- matches the specified 18 pF
- Frequency error
- 0 ppm
- from the capacitor value; the crystal's own tolerance adds
- Trim sensitivity
- 10 to 30 ppm/pF
- typical for small MHz crystals
- Critical gm
- 0.505 mA/V
- 4 × ESR × (2πF)² × (C0 + CL)²
- Gain margin
- 19.8
- 10 mA/V / critical gm; must be above 5
- Drive level
- -
- has to be measured: enter the swing
The link reproduces these exact inputs - paste it in a design review or a pull request.
Bring the crystal, the MCU and the accuracy the product needs. We will look at the oscillator with you (crystal choice, load, gain margin, layout around the pins) before the board goes to fab. If you need the whole board done, see PCB design and layout services.
Load capacitors for common crystal CL values
C1 = C2 for each common load capacitance at 3 pF and 5 pF of stray, as the nearest E24 value, with the load that value presents in brackets. The table follows the capacitor series you selected above. Values under 3 pF are where the stray estimate decides the frequency more than the capacitor does.
| Crystal CL | C1 = C2 at 3 pF stray | C1 = C2 at 5 pF stray |
|---|---|---|
| 6 pF | 6.2 pF (6.1 pF) | 2 pF (6 pF) |
| 7 pF | 8.2 pF (7.1 pF) | 3.9 pF (6.95 pF) |
| 8 pF | 10 pF (8 pF) | 6.2 pF (8.1 pF) |
| 9 pF | 12 pF (9 pF) | 8.2 pF (9.1 pF) |
| 10 pF | 15 pF (10.5 pF) | 10 pF (10 pF) |
| 12 pF | 18 pF (12 pF) | 15 pF (12.5 pF) |
| 12.5 pF | 20 pF (13 pF) | 15 pF (12.5 pF) |
| 16 pF | 27 pF (16.5 pF) | 22 pF (16 pF) |
| 18 pF | 30 pF (18 pF) | 27 pF (18.5 pF) |
| 20 pF | 33 pF (19.5 pF) | 30 pF (20 pF) |
The equation
A crystal is cut and calibrated to hit its nominal frequency with one specific capacitance across it: the load capacitance CL in its datasheet. In a Pierce oscillator, the circuit inside nearly every MCU, the crystal sees C1 and C2 in series, plus whatever the pins, pads and traces add: CL = (C1 × C2) / (C1 + C2) + Cstray. With two equal capacitors that rearranges to C1 = C2 = 2 × (CL - Cstray). The calculator rounds to the nearest standard value, taking the higher one on a tie because a crystal is less sensitive on the high side, and then reports the load that value really presents. Cstray here is one lumped figure in parallel with the crystal, the convention of ST's application note AN2867. If your number is the capacitance from each pin to ground, enter half of it.
The stray capacitance is the number you are guessing
Everything else in the equation comes from a datasheet. Stray capacitance comes from your layout: the MCU pins, the pads, the trace length and the planes under them, typically 2 to 5 pF in total. A 1 pF error in that guess is a 1 pF error in the load, the same as fitting capacitors 2 pF off. That is why the first boards deserve a frequency measurement: read the clock from a buffered output pin or a timer with a frequency counter, never with a probe on the crystal pins, because the probe adds more capacitance than you are trying to resolve. If the crystal runs fast, the load is too low and the capacitors go up; if it runs slow, they come down. With the motional capacitance Cm entered, the calculator turns each pF of mismatch into ppm using S = Cm / (2 × (C0 + CL)²), which comes out in ppm per pF as 500 × Cm / (C0 + CL)² when Cm is in fF and the capacitances are in pF. Without Cm it shows a typical band: roughly 10 to 30 ppm per pF for small MHz crystals.
Gain margin decides whether it starts at all
The right capacitors do not help if the oscillator cannot sustain the crystal. The crystal needs a minimum transconductance from the amplifier, gm_crit = 4 × ESR × (2πF)² × (C0 + CL)², and AN2867 asks for the oscillator's gm to be more than five times that. The worked example in the application note is an 8 MHz crystal with 80 Ω ESR, 7 pF of shunt capacitance and a 10 pF load: gm_crit is 0.234 mA/V, and an oscillator with 25 mA/V has a margin of 107. MHz crystals on a general-purpose MCU usually pass easily. The 32.768 kHz oscillator is the opposite case: ESR of 50 to 90 kΩ against a low-power amplifier with a few µA/V. With 70 kΩ and 1.2 pF of shunt capacitance, a 12.5 pF crystal needs 3.6 times the gm a 6 pF crystal does. Use the maximum ESR from the datasheet, not the typical figure, and remember that a series resistor added to limit drive level counts as ESR in this check.
Drive level has to be measured
Drive level is the power dissipated in the crystal, DL = ESR × Irms², and the crystal datasheet gives a maximum: often 100 µW or a few hundred µW for a MHz crystal, and around 1 µW or less for a watch crystal. Overdriving ages the crystal faster and can damage a tuning-fork crystal outright. It cannot be predicted from the datasheets alone, because the swing depends on the oscillator's amplitude control, so this page only calculates it from a measurement. AN2867's method: measure the peak-to-peak swing at the oscillator input capacitor with a low-capacitance probe, take the crystal current as the current through that capacitor, Irms = 2πF × Vrms × Ctot with Ctot = C1 + Cstray / 2 + Cprobe, and so DL = ESR × (π × F × Ctot)² × Vpp² / 2. For the 8 MHz preset with 30 pF capacitors, a 1 pF probe and 1 V peak to peak, that is 26.7 µW. If the result is above the crystal's limit, add a series resistor at the oscillator output and run the gain margin check again.
Frequently asked questions
What load capacitors for an 8 MHz crystal with 18 pF CL?
Two 30 pF C0G capacitors, if the board adds about 3 pF of stray capacitance: C1 = C2 = 2 × (18 - 3) = 30 pF, a standard E24 value that loads the crystal with exactly 18 pF. With 5 pF of stray the ideal is 26 pF and the nearest standard value is 27 pF, which presents 18.5 pF. If you only stock E12 values, a pair of 33 pF presents 19.5 pF, while one 27 pF and one 33 pF present 17.85 pF, which is closer. The common habit of fitting 22 pF gives this crystal 14 pF, which is 4 pF less than it was calibrated at.
How do I calculate crystal load capacitors?
The crystal sees the two capacitors in series, plus the stray capacitance of the pins and traces: CL = (C1 × C2) / (C1 + C2) + Cstray. With equal capacitors that becomes C1 = C2 = 2 × (CL - Cstray). CL is the load capacitance in the crystal datasheet and Cstray is typically 2 to 5 pF; 3 pF is a reasonable first guess for a compact layout. For a 16 MHz crystal specified at 10 pF with 3 pF of stray the ideal is 14 pF, and 15 pF, the nearest standard value, presents 10.5 pF. Do not fit capacitors equal to CL: two 10 pF parts load that crystal with only 8 pF.
What happens if the load capacitors are wrong?
The oscillator usually still runs, but off frequency: too little capacitance and the crystal runs fast, too much and it runs slow. The error is the mismatch times the crystal's trim sensitivity, S = Cm / (2 × (C0 + CL)²). An 8 MHz, 18 pF crystal with 20 fF of motional capacitance and 7 pF of shunt capacitance moves 16 ppm per pF, so 22 pF capacitors, which give it 14 pF with 3 pF of stray, leave it about 76 ppm fast. That is more than the whole ±50 ppm budget an Ethernet PHY typically allows. On a real-time clock, a 12.5 pF watch crystal fitted with 12 pF capacitors sees 9 pF and runs about 44 ppm fast, which is 3.8 seconds a day. Oversized capacitors also raise the gain the oscillator needs, so start-up gets slower and less reliable.
What capacitors for a 32.768 kHz crystal?
It depends on the load capacitance the crystal was cut for: 6, 7, 9 or 12.5 pF. With 3 pF of stray, a 12.5 pF crystal needs 19 pF, so fit 18 pF or 20 pF (12 pF or 13 pF of load); a 9 pF crystal needs 12 pF; a 7 pF crystal needs 8 pF, so 8.2 pF; a 6 pF crystal needs 6 pF, so 6.2 pF. Check gain margin before you choose the crystal. With 70 kΩ ESR and 1.2 pF of shunt capacitance, a 12.5 pF crystal has a critical gm of 2.23 µA/V and a 6 pF one only 0.615 µA/V, so a low-power oscillator with 5 µA/V has a margin of 2.2 on the first and 8.1 on the second. Many low-power MCUs can only drive the 6 or 7 pF types.
What is gain margin for a crystal oscillator?
It is the ratio of the oscillator's transconductance gm to the minimum the crystal needs to keep oscillating, gm_crit = 4 × ESR × (2πF)² × (C0 + CL)². ST's AN2867 asks for a ratio above 5, so the oscillator still starts across temperature, supply voltage and part-to-part spread. An 8 MHz crystal with 80 Ω ESR, 7 pF of shunt capacitance and an 18 pF load has a critical gm of 0.505 mA/V, so an oscillator with 10 mA/V has a margin of 19.8. The requirement grows with ESR and with the square of both frequency and C0 + CL. Watch crystals are where it fails: their ESR is tens of kΩ and a low-power oscillator has a gm of only a few µA/V. Some datasheets give Gm_crit_max instead; then gm_crit only has to be below that figure.
If the clock is one part of a real board
Two capacitors are a five-minute decision. A clock that starts every time at -40 °C, holds an Ethernet or radio tolerance and keeps time for years on a coin cell is not, and that is our day job: PCB design and layout and firmware development explain how we work. If you are still choosing the part, the MCU selector is next door, and once the clock is settled the STM32 timer calculator and the battery life calculator pick up from there. If a number here decides something real, a free 30-minute technical call is the fastest way to check it against someone who has shipped the board.