SDR and RF Board Design for AD9361, ADRV9361 and Zynq-Based Radios

Who can design a carrier board for an ADRV9361 SoM?

inteRFace R&D designs carrier and interface boards for SDR system-on-modules such as the Analog Devices ADRV9361-Z7035 (an AD9361 transceiver with a Zynq Z-7035) and the ADRV9364-Z7020 (an AD9364 with a Zynq Z-7020). We take the module's connector pinout, power requirements and clocking from the vendor documentation, design the board that carries it into your system, and bring it up on the bench. The work is schematic, layout, power, RF and the bring-up firmware, run by one team so nothing falls between the board designer and the radio engineer.

Typical reasons a team needs one: the vendor's breakout carrier is the wrong size or exposes the wrong I/O, the radio has to fit inside a payload module or an enclosure, the system needs its own power input and protection, or the RF ports need a front end the evaluation carrier does not have. If the radio is going to space, our CubeSat payload electronics page covers the bus interface, rail protection and space practice; for carrier boards around other modules, see SoM carrier board design.

What does an SDR and RF board design engagement cover?

Everything between the transceiver and the connectors your system sees. That usually means the items below, scoped in writing before any work starts so you know which ones are ours and which stay with your team.

• Module integration: the high-density board-to-board connectors, the module's power input and power-good handshakes, boot mode, JTAG and a console port.
• RF front end: filters, low-noise amplifiers, power amplifiers, transmit/receive switching, baluns and matching to the transceiver's differential ports, and the 50-ohm routing to the connectors.
• Clocking: a reference that can follow an external 10 MHz, PPS for time alignment, a clean clock buffer and the distribution to every device that needs it.
• Power: input protection, low-noise rails for the RF sections, switching regulators placed and frequency-planned so their harmonics stay out of the band you care about.
• Digital I/O: Ethernet, USB, UART, GPIO, I2C and SPI to the host, plus any custom signals your system needs, with level shifting and protection.
• Mechanical fit: board outline, connector placement, shielding cans, mounting and the thermal path for the Zynq and any power amplifier.

Should you build on an SDR module or put the AD9361 on your own board?

For most first products and instruments, build on a module. A module such as the ADRV9361-Z7035 already solves the hardest layout on the board, the transceiver, the Zynq and its DDR, and it arrives with Analog Devices' open-source HDL reference design and Linux IIO drivers, so your team starts from a radio that already receives. A chip-down design, with the AD9361 or AD9364 and an FPGA on your own board, starts to make sense when the volume is high enough to pay for the extra engineering, when the module's size or power will not fit, or when you need a front end so tightly integrated that a connector between it and the transceiver costs you performance. We will tell you which side of that line your project is on before you pay for either.

How do you design the RF front end around an AD9361 or AD9364?

Start from the link budget, not the parts catalog. The AD9361 (two transmit and two receive channels) and the AD9364 (one of each) tune from 70 MHz to 6 GHz, which is a reason to use them and a reason the front end must be specific: the filters, amplifiers and switches are chosen for the bands you actually operate in, the noise figure and blocking you need, and the transmit power the application calls for. The board then has to deliver that design: controlled-impedance lines on a stackup agreed with the fabricator, grounded coplanar waveguide with via fencing where isolation matters, shielding over the sensitive sections, and RF test points so each stage can be measured on its own.

Impedance is calculated with the fabricator's real dielectric data, not a datasheet default. For a first check of a 50-ohm line on your stackup, the free Microstrip Impedance Calculator runs the IPC-2141 equations in both directions; the final widths come from the fabricator's field solver. Whether the board needs a hybrid stackup with a low-loss laminate depends on frequency and loss budget, and we make that call with you rather than defaulting to the expensive answer.

How do you lock an SDR to a 10 MHz reference and PPS?

By designing the reference path on the carrier: an input for an external 10 MHz, usually from a GNSS-disciplined oscillator, conditioned and multiplied to the frequency the transceiver and the FPGA expect, plus a PPS input routed to the programmable logic so samples can be timestamped against it. The design choices are the ones that decide phase noise and time alignment: the clock buffer and PLL, termination, the trace length to each consumer, and isolation from switching supplies. When several radios have to stay coherent, the same 10 MHz and PPS are fanned out to every unit, and the board is laid out so the distribution adds as little skew and noise as possible.

What does bring-up of an SDR carrier board involve?

Bring-up proves the board in a fixed order, so each step rests on the one before: power rails and sequencing, the module booting and the console alive, JTAG access, the reference clock locked, the transceiver talking to its driver, then receive and transmit measured in each band you specified. The software side usually starts from Analog Devices' reference design and Linux drivers, which lets the radio be checked in GNU Radio, MATLAB or Python through libiio within days of first power. Every measurement goes into a bring-up report with the method written down, so your team can repeat it on the next unit and on the production line.

Custom signal processing in the FPGA fabric, beyond integrating the reference design, is scoped separately. If your waveform needs it, we say on the first call whether it belongs in our quote or with your DSP team, and we design the carrier so either path works.

How much does an SDR carrier board cost to develop?

Priced in engineering hours; you get a written quote with phases before any work starts. As a typical range from our published PCB design figures, complex 6-8 layer high-speed boards with an SoC run 140-440 engineering hours, and boards with a discrete RF front end go beyond that, so an SDR carrier sits at or above that band depending on how much of the RF chain lives on it. The drivers of cost are the number of RF paths and bands, the clocking requirements, the environment the board must survive and how far the bring-up has to go. For a planning number on your scope, run it through the free project cost estimator or the AI estimator on the homepage, and see how much PCB design costs for the tiers behind the numbers.

How does an SDR board design project start?

With a free 30-minute call with a senior engineer: book a time and bring the module part number, the bands, the interfaces your system needs and the envelope it has to fit. A mutual NDA is signed before any technical detail is exchanged, you keep 100% of the IP, and inteRFace R&D never takes equity. The first paid step is a bounded architecture review: block diagram, front-end and clocking plan, power tree, connector and mechanical plan, the risks ranked, and a written quote with phases for the work that follows. If the radio or its data is export-controlled, raise it on that first call; classification is checked at project start, before any files change hands.

We are based in Silicon Valley and work with teams across the United States, mostly remotely: design reviews on video with the board on camera, boards shipped by carrier. When the firmware on the radio is the larger part of the job, our embedded firmware development page describes that engagement, and the general board process is on the PCB design page.