SoM Carrier Board Design for Zynq, i.MX, Jetson and Compute Module

Who designs custom carrier boards for system-on-modules?

inteRFace R&D designs custom carrier boards for system-on-modules: the board a SoM plugs into, which gives it power, connectors, interfaces and a place in your product. We take the module vendor's design guide and reference carrier, strip it down to the interfaces your product actually uses, add the power input, protection and connectors your system needs, lay it out to the module's high-speed rules, and bring it up through boot to a working Linux console. Embedded Linux on i.MX and Raspberry Pi class hardware is part of our regular work, and the board, the bring-up and the board support package changes are done by one team.

For a software-defined radio module such as the ADRV9361-Z7035, the RF and clocking side is covered on our SDR and RF board design page; for a carrier that flies inside a spacecraft payload, see CubeSat payload electronics.

Which SoMs do you design carrier boards for?

• AMD Zynq-7000 and Zynq UltraScale+ MPSoC modules, including the Kria K26 and modules from third-party vendors, with the PL I/O banks, transceivers and their voltage rules respected.
• NXP i.MX modules (i.MX 6, i.MX 8M family, i.MX 93 class) from module vendors, with display, camera, Ethernet and USB brought out as the product needs.
• NVIDIA Jetson modules, such as the Jetson Orin Nano and Orin NX on their 260-pin SO-DIMM connector, with the camera, PCIe and display interfaces and the power the module draws under load.
• Raspberry Pi Compute Module 4 and Compute Module 5, on their two 100-pin high-density connectors, for products that want the Raspberry Pi software ecosystem in a custom board.
• Analog Devices RF SoMs such as the ADRV9361-Z7035 and ADRV9364-Z7020, which combine an AD9361 or AD9364 transceiver with a Zynq.

If you have not chosen the module yet, we compare candidates against your compute, interfaces, power, lifecycle and supply, and the free MCU Selector shows how we score when a microcontroller might be enough.

Carrier board or chip-down design: which is right?

For first products and moderate volumes, usually a carrier board. The module carries the parts of the design that are hardest to get right, the processor, DDR memory, the PMIC and often eMMC and Wi-Fi, already validated, so the carrier is a simpler board with a shorter path to a working unit. Chip-down, with the processor and memory on your own board, pays off when volumes are high enough that the module's price premium outweighs the extra engineering and validation, or when size, power or cost targets cannot be met with a module. The crossover depends on the module price and your volume, and we will work it out with your numbers rather than a rule of thumb.

What makes a SoM carrier board harder than it looks?

Three things: the connector, the power and the high-speed signals. A high-density mezzanine or SO-DIMM connector has a footprint, mating height and coplanarity tolerance that leave no room for a guessed land pattern, and its pins have current ratings the power design must respect; mechanical retention against vibration matters as much as the electrical pinout. The power has to arrive in the order and at the time the module requires. And the interfaces leaving the module, such as PCIe, USB 3, MIPI CSI-2 and DSI, gigabit Ethernet and HDMI, are differential pairs with impedance and length rules the carrier must keep from the connector pin to the outside world.

How do you handle power sequencing on a carrier board?

By following the module's power-up and power-down requirements exactly and making sure nothing on the carrier violates them. The carrier supplies the module's input rail with the current headroom and transient response it needs, drives the module's enable and reset lines, and waits for its power-good before powering the peripherals that depend on it. Equally important is what happens while the module is off: carrier devices must not back-power the module through its I/O, so peripherals are switched with the module's rails or isolated by buffers that go high-impedance when unpowered. Input protection, inrush limiting and a clean shutdown path for power loss complete the design. For a linear rail on the carrier, the free LDO Thermal Calculator shows quickly whether it will run too hot.

How do you design boot, JTAG and console access?

So that a board that will not boot can still be diagnosed and recovered. Every carrier gets the module's boot-mode straps brought to resistors or switches, its USB or serial recovery path accessible (force-recovery on Jetson, USB boot on the Compute Module, serial download on i.MX, JTAG and boot-mode selection on Zynq), a debug console through a USB-to-UART bridge, and a JTAG header or a footprint for a cable-less debug connector. The production version can hide these behind test pads, but they are never removed, because the unit that fails in the field is the one you most need to talk to.

How do you route controlled-impedance interfaces on a carrier?

With a stackup agreed with the fabricator before routing, and the module vendor's rules for each interface. Differential pairs are routed to their target impedance (typically 85, 90 or 100 ohms depending on the standard), length-matched within each pair and between pairs where the standard needs it, kept over unbroken reference planes, with AC-coupling capacitors, ESD protection and connectors chosen for the data rate. Single-ended lines get the same care; the free Microstrip Impedance Calculator gives a first answer for a single-ended trace on your stackup, and the fabricator's field solver sets the final widths. Signal-integrity checks on the fastest nets happen before fabrication, not after.

What does a SoM carrier board cost to develop?

Priced in engineering hours; you get a written quote with phases before any work starts. As a typical range from our published PCB design figures, a standard 4-layer mixed-signal board runs 50-140 engineering hours and complex 6-8 layer high-speed work 140-440; a carrier lands in one band or the other depending on how many high-speed interfaces it brings out. For calibration from delivered work, a Raspberry Pi 5 GPIO adapter board, schematic through released production files, took about 55 hours. Device-tree and board-support changes are quoted as their own phase. For a planning number, run your scope through the free project cost estimator or the AI estimator on the homepage.

What do you receive from a carrier board project?

• Schematic and layout sources, Gerbers, drill and pick-and-place files, and a costed bill of materials with alternates for anything single-sourced.
• The stackup and impedance table agreed with the fabricator, and the interface checklist against the module vendor's design guide.
• A bring-up report: power sequencing measured, boot, console, JTAG and every interface verified, with the method written down.
• Device-tree and board-support changes for the carrier, in your repository, when they are in scope.
• A production test plan your contract manufacturer can run.

How does a carrier board project start?

With a free 30-minute call with a senior engineer: book a time and bring the module you are using or considering, the interfaces you need, and the enclosure or envelope the board must fit. A mutual NDA is signed before any technical detail is exchanged, you keep 100% of the IP, and inteRFace R&D never takes equity. The first paid step is a bounded architecture review: block diagram, power tree and sequencing plan, connector and mechanical plan, the risks ranked and a written quote with phases. We are based in Silicon Valley and work with teams across the United States, mostly remotely. The board process itself is described on our PCB design page, and the Linux and firmware side on embedded firmware development.